1. Field of the Invention
The present invention relates to a semiconductor device including a flash memory and the like, and to a fabrication method therefor.
2. Description of the Background Art
Generally, a semiconductor device including a flash memory and the like has regions; a memory cell section and a peripheral circuit section on a surface of a semiconductor substrate thereof. Necessary electrodes and wirings are formed in each of the regions and furthermore, an isolation oxide film for use in electrically partitioning the surface of the semiconductor substrate is formed therein. Upon forming the isolation oxide film, there have been employed a trench isolation scheme (STI: Shallow Trench Isolation) and a LOCOS (Local Oxidation of Silicon) scheme. In a case where the isolation oxide film is fabricated by one of the schemes, a phenomenon called dishing in which a central part of an isolation oxide film is depressed sometimes occurs. FIG. 14 shows an example the dishing occurs. In the example of FIG. 14, the dishing occurs on isolation oxide film 2 formed on semiconductor substrate 1. Moreover, as shown in FIG. 15, as a result of locally forming gate electrodes 10 in a peripheral circuit section in order to fabricate transistors 4, there arise differences between heights of the top surfaces of the electrodes thereof above the surface of semiconductor substrate 1 in the peripheral circuit section.
In such a case where there exist a part in which dishing occurs and parts having largely different heights from each other, a level difference 6, as shown in FIG. 15, sometimes takes place on the top surface of an interlayer insulating film 5 formed on an area including the parts so as to cover thereon. Moreover, even if interlayer insulating film 5 was formed to be flat at first sight, a level difference sometimes occurs on the top surface of interlayer insulating film 5 revealed after a CMP (Chemical Mechanical Polishing) process conducted for planarization of the top surface of interlayer insulating film 5 at a stage prior to formation of a contact hole in interlayer insulating film 5 under an influence of a level difference of a structure below interlayer insulating film 5. It is problematic in subsequent steps to produce such a level difference on the top surface of interlayer insulating film 5.
In order to reduce a level difference produced on the top surface of interlayer insulating film 5 in the peripheral circuit section, it has been proposed to arrange dummy electrodes 13 in the neighborhood of each gate electrode 10 arranged in the peripheral circuit section as shown in FIG. 16. While an isolation oxide film is omitted in FIGS. 15 and 16, in a case where an isolation oxide film is available in the neighborhood of transistor 4, a scheme has been adopted in which isolation insulating film 2, as shown in FIG. 17, is divided into plural pieces of a size of the order at which dishing is hard to occur thereon to form dummy electrodes 13 so as to span dummy electrodes.
On the other hand, in a case where a flash memory 3 is placed in the memory cell section, flash memory 3 adopts a two-layer structure as shown in FIG. 16 obtained by stacking a floating electrode 11 and a control gate 12 on semiconductor substrate. In contrast to this, in the peripheral circuit section, electrodes are only of a single layer structure; therefore parts of the electrodes in the peripheral circuit section have been lower as compared with parts of the two-layer structures in the memory cell section, though with a reduced level difference 6. As a result, a level difference 7 has remained between the memory cell section and the peripheral circuit section.
It is an object of the present invention to provide a semiconductor device having a structure capable of further reducing a level difference produced on the top surface of an interlayer insulating film, and a fabrication method therefor.
In order to achieve the above-mentioned object, one aspect of a semiconductor device according to the present invention includes: a semiconductor substrate having a memory cell section and a peripheral circuit section defined in a plane; a floating gate electrode formed on the semiconductor substrate in the memory cell section; a control gate electrode laminated above the floating gate electrode; a peripheral circuit electrode formed in one-layer-structure on the semiconductor substrate in the peripheral circuit section; a first dummy electrode formed on the semiconductor substrate in the peripheral circuit section so as to have approximately same thickness as the floating gate electrode; and a second dummy electrode laminated above the first dummy electrode so as to have approximately same thickness as the control gate electrode. With the construction adopted, a composite dummy electrode is also provided in a two-layer structure in the peripheral circuit section in a manner similar to a two-layer structure of a composite electrode for use in a flash memory and the like in the memory cell section, therefore, enabling reduction in a level difference on the top surface of an interlayer insulating film formed on the top sides of the memory cell section and the peripheral circuit section.
In order to achieve the object, another aspect of the semiconductor device according to the present invention includes: a semiconductor substrate having a memory cell section and a peripheral circuit section defined in a plane; a floating gate electrode formed on the semiconductor substrate in the memory cell section; a control gate electrode laminated above the floating gate electrode; a peripheral circuit electrode formed in one-layer-structure on said semiconductor substrate in the peripheral circuit section; a contact receiving portion formed on the semiconductor substrate in the peripheral circuit section, and connected to the peripheral circuit electrode; and a third dummy electrode formed between the contact receiving portion and the semiconductor substrate. With the construction adopted, the third dummy electrode interposes below the contact receiving portion to thereby form a two layer structure at the contact receiving portion and to ensure a height of the contact receiving portion to be the same as that of the composite electrode of a two-layer structure for use in a flash memory and others in the memory cell section, thereby reducing a level difference produced on the top surface of the interlayer insulating film.
In order to achieve the object, a fabrication method for a semiconductor device according to the present invention is directed to a method for fabricating a semiconductor device which includes a semiconductor substrate having a memory cell section and a peripheral circuit section defined in a plane; wherein the memory cell section having a floating gate electrode and a control gate electrode; wherein the peripheral circuit section having a gate electrode in one-layer-structure and dummy electrodes in two-layer-structure; and includes the following steps: a first conductive layer forming step of collectively forming a first conductive layer including a portion to be served as a floating gate electrode in a memory cell section, across the memory cell section and the peripheral circuit section; a second conductive layer forming step of collectively forming a second conductive layer including a portion to be served as a control gate electrode laminated above the floating gate electrode in the memory cell section above the first conductive layer, across the memory cell section and the peripheral circuit section; a first conductive layer patterning step of patterning not only the floating gate electrode on the first conductive layer at a portion thereof located in the memory cell section, but also the first dummy electrode on the first conductive layer at a portion thereof located in the peripheral circuit section; and a second conductive layer patterning step of patterning not only the control gate electrode on the second conductive layer at a portion thereof located in the memory cell section, but also the second dummy electrode on the second conductive layer at a portion thereof located in the peripheral circuit section; and a step of forming interlayer insulating film to cover the memory cell section and the peripheral circuit section collectively. With the method adopted, the same layer laminating step and the same etching step can be used commonly for the first and second conductive layers to thereby form the composite electrode in the memory cell section and the composite dummy electrode in the peripheral circuit section in parallel; therefore, enabling achievement of a construction with a composite dummy electrode without increasing useless steps.